1. Field of the Invention
The present invention generally relates to decoder/driver circuits for static memories and, more particularly, to word line decoder/driver circuits capable of extremely fast operation and wide word line voltage swings.
2. Description of the Prior Art
Electronic memory circuits have been known for many years. Such memory circuits have employed a wide variety of types of circuits and circuit elements in order to store information in some way, such as by storage of charge in a capacitive element or the use of a bistable circuit or element. Such a bistable element can take the form, for example, of the well-known flip-flop circuit, where a pair of transistors are cross-coupled in such a way that when one transistor is turned on, the other will be forced off, or a magnetizable core or other element or domain which can be selectively magnetized into one of at least two distinct states.
Each of these memory types, categorized by the type of memory cell employed, has distinct advantages and disadvantages with respect to the other types of memory and each type will typically be applied where the advantages can be best utilized. In particular, static random access memories using bistable circuits constructed from bipolar transistors are typically used in cache memories and central processing units due to their characteristically high speed. The access cycle times of such devices can be as short as 3 ns, or more than an order of magnitude faster than dynamic RAMs, due largely to their lack of need for refresh and inherently faster operation of sense amplifiers since detection of data in a bistable circuit of a static RAM is far easier than detection of a minuscule amount of electrical charge in a capacitive memory cell of a dynamic RAM.
To fully exploit the potential speed of static RAMs, it is necessary to produce a wide voltage swing on a word line of the memory at high speed. The voltage swing must be large to provide sufficient voltage margins for various memory operations. Developing sufficiently large voltage swings at high speed is complicated by the capacitance of the word lines and the need to limit current within the device to minimize the power dissipation of the memory.
Since the practical length of word lines is limited by the capacitance which can be tolerated and the number of memory cells which can be coupled to a word line is limited by the physical size of the memory cells and the practical word line length, many word line drivers are required for memories of even modest size. As more memory cells are integrated on a single chip, it becomes more critically necessary to simplify the decoder word line driver circuits to allow more word line decoder/driver circuits to be placed on a chip and to further limit the stand-by current thereof.
In this regard, it should be noted that to obtain high switching speed, consistent with low stand-by current, it is often necessary to provide two stage decoders to obtain sufficiently large voltage swings to provide adequate base drive current for the word line driver transistors. Large voltage swings are needed in order to achieve sufficiently high currents through the word line driver transistors for the capacitive load presented by the word lines. This requirement also has prevented the reduction in the element count of the word line driver circuits. Further, the degree of speed increase possible by the use of two stage decoders is limited by the delay inherent in propagation of a signal through an increased number of stages.
So-called Darlington-connected transistor amplifiers are well known and are often employed in memory driver circuits because of their high speed, simplicity and integration compatibility with other components. In some word line drivers, Darlington circuits are used as direct drive for the word lines because of their high current carrying capability when relatively large values of power supply voltage are available. More recently, as disclosed in related co-pending application Ser. No. 07/651,680 by Joseph Y. Wong, entitled HIGH-SPEED, LOW-POWER PNP-LOADED WORD LINE DECODER/DRIVER CIRCUIT, assigned to the assignee of the present invention and hereby incorporated by reference, a Darlington circuit is used as the first stage of the decoder/driver, while a half current switch is used as the second stage to provide a full word line voltage swing.
However, unless operated at saturation or cut-off, Darlington-connected amplifiers have a high power dissipation which is undesirable in an integrated circuit having large number of such devices. It is also undesirable for saturation to occur in a high speed device since saturation increases parasitic capacitances and degrades switching speed. Therefore, the use of Darlington circuits in memory devices has usually been used to provide additional pull-up speed or additional current capacity only for an extremely short period of time at the beginning of a select period such as in the circuit of FIG. 1 which will be discussed in detail below.